Category Archives: Tin công nghệ

AXI-to-APB Bridge

DTI AXI2APB is bridge to convert AXI command into APB command. The bridge is fully programmable and configurable, flexible to customer’s needs
Download Product Overview

Features Design Status

DTI AXI2APB Controller supports:

  • Asynchronous Reset
  • Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
  • Compliant with APB bus protocol
  • Supports asynchronous clock domain
  • Supports narrow transfers
  • AXI4 and APB data widths are the same and support upto 256 bits
  • Programmable Registers

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


AXI-to-AHB Bridge

DTI AXI2AHB is bridge to convert AXI command into AHB command. The bridge is fully programmable and configurable, flexible to customer’s needs
Download Product Overview

Features Design Status

DTI AXI2AHB Controller supports:

  • Asynchronous Reset
  • Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
  • Compliant with AHB 5C bus protocol
  • Supports asynchronous clock domain
  • Supports narrow transfers
  • AXI4 and AHB data widths are the same and support upto 256 bits
  • Programmable Registers

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


SPI-to-UART Bridge

DTI_SPI2UART is a bridge that converts data between SPI and UART standards

Features Design Status
  • Compliant with SPI and UART Protocol
  • Programmable data length UART (8 bits)
  • Programmable 1, 2 bit Stop
  • Programmable Data Direction (LSB first or MSB first)
  • Programmable Clock polarity and phase (CPOL and CPHA) – 4 mode
  • Programmable parity mode
  • Configurable oversampling support (8x, 16x)

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo


Quad SPI Controller

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.

Download Product Overview

Features Design Status
DTI Quad-SPI Controller supports:

  • Supports flash devices from Micron, Macronix, …
  • Supports QPI PSRAM devices from Apmemory
  • Supports Single/Dual/Quad SPI protocols
  • Supports Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
  • Support APB, AHB and AXI interfaces
  • Programmable FIFO watermarks
  • Supports three operating modes: Indirect mode, Memory-mapped mode, Status-flag polling mode
  • Interrupt and DMA handler
  • Data prefetching in Memory-mapped mode
  • Support 8/16/32/64 Bytes Wrapped Burst operation (AHB/AXI interface)
  • PHY interface with delay locked-loop

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


SPI-to-I2C Bridge

DTI_SPI2I2C is a bridge that converts data between SPI and I2C standards

Features Design Status
  • SPI clocking modes 0, 1, 2, and 3 are supported
  • Programmable Clock polarity and phase (CPOL and CPHA)
  • Transfer data bit MSB first
  • I2C-bus slave interface operating up to 400 kHz
  • Uses 7-bit slave addressing
  • Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified on runtime-changeable levels

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo


Octa SPI Controller

Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.

Download Product Overview

Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI Octal-SPI Controller supports:

  • JEDEC xSPI standard compliant
  • Supports flash devices from Micron, Macronix, Spansion …
  • Supports PSRAM devices from Apmemory
  • Supports Single/ Octal SPI protocols
  • Support APB, AHB and AXI interfaces
  • Single and double transfer rate
  • Programmable FIFO watermarks
  • Supports three operating modes: Indirect mode, status-flag polling mode, memory-mapped mode
  • Interrupt and DMA handler
  • Data prefetching in memory-mapped mode
  • Support AHB, AXI and device wrapping bursts
  • PHY interface with delay locked-loop

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


Real Time Clock (RTC)

Dolphin Technology provides Real Time Clock (RTC) IP which is used to avoid confusion with ordinary hardware clocks which are only signals that govern digital electronics, and do not count time in human units. The IP is a low-power, cost-effective solution for demanding applications and offers SoC integrators the advanced capabilities and support the requirements of high-performance designs and implementations.

Download Product Overview

Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI RTC Controller supports:

  • Master only operation
  • Slave only operation
  • Master and slave operation
  • Clock synchronization
  • Programmable FIFO watermarks
  • Interrupt interface

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo

 


SPI Controller

Dolphin Technology provides Serial Peripheral Interface (SPI) IP which enables an AHB/APB host to access a serial device at high-speed through the SPI interface. The controller supports both Master and Slave modes and consists of a DMA controller to enhance the system performance. The IP can be used in applications such as flash memory card and digital camera.

Download Product Overview

Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI SPI Controller supports:

  • Programmable operation mode: master or slave
  • Programmable data length (8, 16, 24, 32 bits)
  • Programmable Clock polarity and phase (CPOL and CPHA)
  • Programmable Data Direction (LSB first or MSB first)
  • Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified runtime-changeable levels
  • Programmable to use FIFO interrupt
  • Programmable Clock Divider
  • Support Multiple Slaves
  • Support Delay between Slave Select and Serial Clock, Delay between 2 bytes in a transfer
  • Clock synchronization

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


Welcome to the ‘Siliconomy’ – Nền kinh tế bán dẫn

Trí tuệ nhân tạo đại diện cho sự chuyển đổi thế hệ trong lĩnh vực điện toán đang tạo ra Siliconomy được kỳ vọng sẽ tạo ra những bứt phá cho kinh tế xã hội của nhân loại. Tất cả đều phụ thuộc vào năng lực tính toán của những con chip tối tân trong các thiết bị điện tử máy tính. Việt nam đang nổi lên là điểm đến lý tưởng cho các công ty thiết kế vi mạch. Hãy đến với Dolphin Technology Vietnam để cùng tìm hiểu và nắm bắt thời cơ vàng để bắt đầu sự nghiệp vi mạch.


Reed-Solomon Encoder/Decoder


DTI Reed Solomon Encoder and DTI Reed Solomon Decoder are used in error correction applications using Reed-Solomon codes. These IPs are fully programmable, configurable and flexible to customers’ needs.

Features

  • Fully parameterized Reed-Solomon function, including:
    • Number of bits per symbol
    • Number of symbols per message
    • Number of correctable error symbols per codeword
  • The maximum degree of Galois field can support is 16
  • Automatically configured by customers’ entered parameters
  • Support shortened codewords
  • Encoder features support:
    • Either continuous or discrete operation with chip enable signal
  • Decoder features support:
    • Two decoding algorithms (Berlekamp-Massey and Euclidean)
    • Pipeline operation mode
    • Control input of data to decoder with chip enable signal
    • Error measurement information
    • Separate FIFO memory for increased flexibility

FPGA Demo


Tìm kiếm