Dolphin Technology maintains a broad portfolio of System-On-Chip (SOC) building blocks that provide our clients with solutions ranging from high performance Standard Cell libraries to General Purpose I/O, Special Purpose I/O, Memory Compilers, specialty memory, DRAM controller, DRAM DDR PHY, and PLL/DLL solutions. Our extensive offering has met the most rigorous standards of the industry’s most demanding companies.
Dolphin Technology maintains a broad IP portfolio of Memory Compilers, Specialty Memory and Memory Test & Repair (Memory BIST), providing SoC designers with solutions optimized for low power, high performance and high density across a broad range of process technologies. These solutions feature advanced power management capabilities – such as light sleep, deep sleep, power gating, dual rails and more – that meet even the most demanding low-power, low-leakage requirements. We currently support memories with the following foundries.
TSMC – Memory Compilers & Specialty Memory
Dolphin’s Memory Compilers and Specialty Memory (ROM, Multi-Port RF, CAM, etc.) for TSMC utilize highly optimized memory blocks assembled by our veteran team of memory design experts. These memories have been successfully proven in many generations of silicon, and are currently used by many of the world’s premier technology companies. TSMC compilers are available in the following technology levels:
Dolphin Technology offers one of the industry’s largest selections of Interface IP, all of which has been optimized for ultra high performance across all processes supported. Our I/O portfolio includes:
- Standard I/O (General Purpose I/O or GPIO)
- Specialty I/O (bus-specific I/O)
- NAND Flash I/O
- DDR4/3/2 & LPDDR3/2 I/O
We specialize in Staggered, Inline and Flip Chip pads with aggressive pitch for the most demanding designs, whether pad or core limited. Plus, our I/O Compiler enables us to customize the entire library based on process-specific and chip-specific options.
Dolphin’s core team of experienced I/O design veterans has created an extensive offering of highly optimized I/O blocks that have been successfully proven in many generations of silicon, and are used by some of the world’s largest technology companies. These products are currently available in the following technology levels:
Dolphin offers an extensive array of Standard Cell libraries that have been methodically tested and verified in silicon for each process technology supported. More than 5000 fully customizable cells are available, and each one has been optimized for speed, routability, power and density, in order to maximize performance and wafer yield while lowering overall SoC cost.
Depending on the process technology selected, Dolphin’s Standard Cell libraries are available in Multi-VT (SVT, HVT, LVT) and Multi-channel, and are designed to meet a wide range of application requirements, including:
- 6-track, Ultra High Density (with or without CPODE, 96nm poly pitch)
- 7.5-track, High Performance & High Density (with or without CPODE, 90nm or 96nm poly pitch)
- 9-track, High Performance & Ultra High Density (with or without CPODE, 90nm or 96nm poly pitch)
- 10.5-track, Very High Performance (with or without CPODE, 90nm or 96nm poly pitch)
- 12-track, Ultra High Performance (with or without CPODE, 90nm or 96nm poly pitch)
- Channel Lengths include 16nm, 18nm, 20nm and 24nm
- 6-track available only on 12FFC
Dolphin Technology has assembled a core team of experienced Standard Cell design veterans that have created an extensive offering of highly optimized Standard Cell libraries. These libraries have been successfully proven in many generations of silicon and are currently used by some of the largest technology companies. These are currently available in the following technology levels:
Dolphin’s hardened DDR4/3/2 SDRAM PHY and LPDDR4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin’s DDRx and LPDDRx SDRAM Memory Controller IP.
The hardened PHY macros are currently available in the following technology levels: