Quad SPI Controller

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.

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Features Design Status
DTI Quad-SPI Controller supports:

  • Supports flash devices from Micron, Macronix, …
  • Supports QPI PSRAM devices from Apmemory
  • Supports Single/Dual/Quad SPI protocols
  • Supports Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
  • Support APB, AHB and AXI interfaces
  • Programmable FIFO watermarks
  • Supports three operating modes: Indirect mode, Memory-mapped mode, Status-flag polling mode
  • Interrupt and DMA handler
  • Data prefetching in Memory-mapped mode
  • Support 8/16/32/64 Bytes Wrapped Burst operation (AHB/AXI interface)
  • PHY interface with delay locked-loop

Data Sheets are available under NDA



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