SDRAM DDR Controller


SDRAM DDR PHY

Dolphin’s hardened DDR4/3/2 SDRAM PHY and LPDDR4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).

In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin’s DDRx and LPDDRx SDRAM Memory Controller IP.

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TSMC Technology Levels

The hardened PHY macros are currently available in the following technology levels:

7FF 16FFC 16FF+ 28HPC+
28HPC 28ULP 28HPM 28HPL
28HP 28LP 40G 40LP
40LP_EMF 40ULP 40ULP_EMF 55GP
55LP 55LP_EMF 55ULP 55ULP_EMF
65GP 65LP 65ULP 65ULP_EMF
80GC 80LP 80LP_EMF 90G
90GT 90LP 90LP_EMF 130GS
130LV 130LVOD  180G 180LV
250G

SDRAM DDR Controller

Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.

These Memory Controllers are fully compliant with the DFI 4.0 specification, support speeds up to 4266 Mbps, and are optimized to provide a comprehensive solution when combined with Dolphin’s DDR PHY IP.

>>> Download Product Overview

Features Design Status
  • Supports JEDEC Standard DDR4/3/2 and LPDDR4/3/2 SDRAM
  • DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
  • Supports speeds of up to 4266 Mbps (2133 MHz) LPDDR4
  • Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
  • Built-in Gate Training, Read/Write Leveling, and VREF Training
  • Multi-Port Configurable AXI4 Interface with QoS Signaling
  • Single AXI4-Lite Programming Interface
  • Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
  • Pipeline Option for Frequency versus Latency Tradeoff
  • Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
  • FPGA portable. Compatible with Xilinx PHY and Altera PHY.
  • Available with BFM verification suite.
  • Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
  • Support for Low-Latency Bypass Ports/Channels
  • Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
  • Forward Priority Propagation for Queued Transactions
  • Traffic-Configurable Address Mapping Scheme with Two Column Segments
  • Run-time Configurable Timing Parameters and Memory Settings
  • Intelligent Bank Management and Auto-Precharge Scheduling
  • Intelligent Traffic Direction Aggregation and Switching
  • Programmable and Dynamic Auto-refresh Scheduling
  • Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
  • Real-Time QoS Capability
  • Multi-Channel Configuration (Up to 4)
  • Multi-Rank Configuration (Up to 4)
  • Support for Out-of-Order Memory Access

Data Sheets are available under NDA

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FPGA Demo
DDR3 Controller on Xilinx Board

LPDDR3 Controller on Xilinx Board

DDR3L Controller on Intel Board

DDR4 Controller on Intel Board