Dolphin’s hardened DDR4/3/2 SDRAM PHY and LPDDR4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).
In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin’s DDRx and LPDDRx SDRAM Memory Controller IP.
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TSMC
Technology Levels
The hardened PHY macros are currently available in the following technology levels:
Dolphin Technology offers high performance DDR4/3/2 SDRAM and LPDDR4/3/2 SDRAM Memory Controller IP across a broad range of process technologies.
These Memory Controllers are fully compliant with the DFI 4.0 specification, support speeds up to 4266 Mpbs, and are optimized to provide a comprehensive solution when combined with Dolphin’s DDR PHY IP.
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| Features |
Design Status |
- Supports JEDEC Standard DDR4/3/2 and LPDDR4/3/2 SDRAM
- DFI 4.0 Compliant Interface with 1:1 (Matching), 1:2 and 1:4 Frequency Ratios
- Supports speeds of up to 4266 Mbps (2133 MHz) LPDDR4
- Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
- Built-in Gate Training, Read/Write Leveling, and VREF Training
- Multi-Port Configurable AXI4 Interface with QoS Signaling
- Single AXI4-Lite Programming Interface
- Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
- Pipeline Option for Frequency versus Latency Tradeoff
- Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
- FPGA portable. Compatible with Xilinx PHY and Altera PHY.
- Available with BFM verification suite.
- Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
- Support for Low-Latency Bypass Ports/Channels
- Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
- Forward Priority Propagation for Queued Transactions
- Traffic-Configurable Address Mapping Scheme with Two Column Segments
- Run-time Configurable Timing Parameters and Memory Settings
- Intelligent Bank Management and Auto-Precharge Scheduling
- Intelligent Traffic Direction Aggregation and Switching
- Programmable and Dynamic Auto-refresh Scheduling
- Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
- Real-Time QoS Capability
- Multi-Channel Configuration (Up to 4)
- Multi-Rank Configuration (Up to 4)
- Support for Out-of-Order Memory Access
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Data Sheets are available under NDA
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