EMMC Controller

Dolphin Technology delivers custom, synthesizable IP to support specific design requirements. The DTI EMMC controller provides the logic to integrate a Host and PHY controller supporting embedded MultiMediaCard (eMMC) version 5.1 into any system on chip (SoC).

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Features Design Status

Compliant with the following specifications:

  • JEDEC eMMC Specification Version 5.1.
  • AMBA, Advanced Extensible Interface (AXI) Specification Version 4.0.
  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0.

The Host controller supports:

  • 32-bit and 64-bit system data bus.
  • 32-bit and 64-bit system addressing.
  • 64 and 128 bit DMA Descriptor length.
  • Interrupts functionality.
  • Supports both Asynchronous and Synchronous AXI4 Interface: The Master and the Host Controller operate at the same clock rate or different clock rates.

The data is transferred using:

  • Programmed Input/Output (PIO) mode on the Host Bus Slave interface.
  • Direct Memory Access (SDMA and ADMA2) mode on the Host Bus Master interface.
  • Configurable FIFO size to support different block sizes 512B and 4KB.

eMMC 5.1 features:

  • HS400 high speed interface timing mode of up to 400 MB/s data rate.
  • Transfers the data in HS400, HS200, DDR52, SDR52 modes.
  • 4KB block support.
  • Tuning for HS200 mode.
  • Command Queuing for High Performance data transfers with Hardware Acceleration.
  • Enhanced strobe function for reliable operation at HS400 mode.
  • Host clock rate variable between 0 and 200 MHz.
  • Supports 1-bit, 4-bit and 8-bit data interface.
  • Supports legacy modes (Default Speed, High Speed).
  • CRC7 for command and CRC16 for data integrity.
  • Supports multiple boot mode.

Data Sheets are available under NDA