DDR PHY

Dolphin’s hardened DDR4/3/2 SDRAM PHY and LPDDR5/4x/4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 4266 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST). 

In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin’s DDRx and LPDDRx SDRAM Memory Controller IP.

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TSMC


Technology Levels

The hardened PHY macros are currently available in the following technology levels:

Click on the data for detailed chart

7FF 16FFC 16FF+ 28HPC+
28HPC 28ULP 28HPM 28HPL
28HP 28LP 40G 40LP
40LP_EMF 40ULP 40ULP_EMF 55GP
55LP 55LP_EMF 55ULP 55ULP_EMF
65GP 65LP 65ULP 65ULP_EMF
80GC 80LP 80LP_EMF 90G
90GT 90LP 90LP_EMF  
       
       

 


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