UHS PSRAM Memory Controller

DTI UHS PSRAM external memory controller is interfaced to control PSRAM devices. The controller is fully
programmable and configurable, flexible to customers’ needs.

Features Design Status
  • Single Channel Configuration (1 channel for PSRAM)
  • Single APB Programming Interface (Programming Registers)
  • Single AXI4 Interfaces Configuration (1 AXI4 Interfaces)
  • Programmable Timing Registers
  • Programmable PSRAM Operation Mode (Through MRW)
  • Dynamic Address Mapping Scheme
  • Automatic Periodic Refresh
  • 1:1/1:2/1:4 Frequency Ratio System
  • Asynchronous/Synchronous AXI4/APB Interfaces
  • Page Read Access (PRA) input through DM pin
  • Wrap burst in 16/32/64/128 Bytes length
  • Data write mask for write operation through DM pin
  • PHY features support
    • DFI 3.1 Compliance
    • 1:2 frequency ratio support
    • DDR3/2 LPDDR3/2 PHY- Independent training mode for gate, write leveling
    • 8-bit DQ

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo