Author Archives: Dolphin

AXI-to-APB Bridge

DTI AXI2APB is bridge to convert AXI command into APB command. The bridge is fully programmable and configurable, flexible to customer’s needs
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Features Design Status

DTI AXI2APB Controller supports:

  • Asynchronous Reset
  • Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
  • Compliant with APB bus protocol
  • Supports asynchronous clock domain
  • Supports narrow transfers
  • AXI4 and APB data widths are the same and support upto 256 bits
  • Programmable Registers

Data Sheets are available under NDA

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FPGA Demo


AXI-to-AHB Bridge

DTI AXI2AHB is bridge to convert AXI command into AHB command. The bridge is fully programmable and configurable, flexible to customer’s needs
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Features Design Status

DTI AXI2AHB Controller supports:

  • Asynchronous Reset
  • Compliant with AXI4 (IHI0022J_amba_axi) bus protocol
  • Compliant with AHB 5C bus protocol
  • Supports asynchronous clock domain
  • Supports narrow transfers
  • AXI4 and AHB data widths are the same and support upto 256 bits
  • Programmable Registers

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


SPI-to-UART Bridge

DTI_SPI2UART is a bridge that converts data between SPI and UART standards

Features Design Status
  • Compliant with SPI and UART Protocol
  • Programmable data length UART (8 bits)
  • Programmable 1, 2 bit Stop
  • Programmable Data Direction (LSB first or MSB first)
  • Programmable Clock polarity and phase (CPOL and CPHA) – 4 mode
  • Programmable parity mode
  • Configurable oversampling support (8x, 16x)

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo


Quad SPI Controller

Dolphin Technology provides Quad SPI Controller IP which enables access to a QSPI flash device through read, write and erase operations. The Quad SPI IP either controls a serial data link as a master, or reacts to a serial data link as a slave. The core operates in various data modes from 4 bits to 32 bits. The data is then serialized and then transmitted, either LSB or MSB first, using the standard 4-wire SPI bus interface or the extended Quad mode bus.

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Features Design Status
DTI Quad-SPI Controller supports:

  • Supports flash devices from Micron, Macronix, …
  • Supports QPI PSRAM devices from Apmemory
  • Supports Single/Dual/Quad SPI protocols
  • Supports Single Data Rate (SDR) and Double Data Rate (DDR) data transfers
  • Support APB, AHB and AXI interfaces
  • Programmable FIFO watermarks
  • Supports three operating modes: Indirect mode, Memory-mapped mode, Status-flag polling mode
  • Interrupt and DMA handler
  • Data prefetching in Memory-mapped mode
  • Support 8/16/32/64 Bytes Wrapped Burst operation (AHB/AXI interface)
  • PHY interface with delay locked-loop

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


SPI-to-I2C Bridge

DTI_SPI2I2C is a bridge that converts data between SPI and I2C standards

Features Design Status
  • SPI clocking modes 0, 1, 2, and 3 are supported
  • Programmable Clock polarity and phase (CPOL and CPHA)
  • Transfer data bit MSB first
  • I2C-bus slave interface operating up to 400 kHz
  • Uses 7-bit slave addressing
  • Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified on runtime-changeable levels

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo


Octa SPI Controller

Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.

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Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI Octal-SPI Controller supports:

  • JEDEC xSPI standard compliant
  • Supports flash devices from Micron, Macronix, Spansion …
  • Supports PSRAM devices from Apmemory
  • Supports Single/ Octal SPI protocols
  • Support APB, AHB and AXI interfaces
  • Single and double transfer rate
  • Programmable FIFO watermarks
  • Supports three operating modes: Indirect mode, status-flag polling mode, memory-mapped mode
  • Interrupt and DMA handler
  • Data prefetching in memory-mapped mode
  • Support AHB, AXI and device wrapping bursts
  • PHY interface with delay locked-loop

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


Real Time Clock (RTC)

Dolphin Technology provides Real Time Clock (RTC) IP which is used to avoid confusion with ordinary hardware clocks which are only signals that govern digital electronics, and do not count time in human units. The IP is a low-power, cost-effective solution for demanding applications and offers SoC integrators the advanced capabilities and support the requirements of high-performance designs and implementations.

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Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI RTC Controller supports:

  • Master only operation
  • Slave only operation
  • Master and slave operation
  • Clock synchronization
  • Programmable FIFO watermarks
  • Interrupt interface

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo

 


SPI Controller

Dolphin Technology provides Serial Peripheral Interface (SPI) IP which enables an AHB/APB host to access a serial device at high-speed through the SPI interface. The controller supports both Master and Slave modes and consists of a DMA controller to enhance the system performance. The IP can be used in applications such as flash memory card and digital camera.

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Features Design Status
Compliant with the following specifications:

  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI SPI Controller supports:

  • Programmable operation mode: master or slave
  • Programmable data length (8, 16, 24, 32 bits)
  • Programmable Clock polarity and phase (CPOL and CPHA)
  • Programmable Data Direction (LSB first or MSB first)
  • Use separated Async. FIFO for Transmitting and Receiving Data, with programmable user-specified runtime-changeable levels
  • Programmable to use FIFO interrupt
  • Programmable Clock Divider
  • Support Multiple Slaves
  • Support Delay between Slave Select and Serial Clock, Delay between 2 bytes in a transfer
  • Clock synchronization

Data Sheets are available under NDA

REQUEST NDA

FPGA Demo


UHS PSRAM Memory Controller

DTI UHS PSRAM external memory controller is interfaced to control PSRAM devices. The controller is fully
programmable and configurable, flexible to customers’ needs.

Features Design Status
  • Single Channel Configuration (1 channel for PSRAM)
  • Single APB Programming Interface (Programming Registers)
  • Single AXI4 Interfaces Configuration (1 AXI4 Interfaces)
  • Programmable Timing Registers
  • Programmable PSRAM Operation Mode (Through MRW)
  • Dynamic Address Mapping Scheme
  • Automatic Periodic Refresh
  • 1:1/1:2/1:4 Frequency Ratio System
  • Asynchronous/Synchronous AXI4/APB Interfaces
  • Page Read Access (PRA) input through DM pin
  • Wrap burst in 16/32/64/128 Bytes length
  • Data write mask for write operation through DM pin
  • PHY features support
    • DFI 3.1 Compliance
    • 1:2 frequency ratio support
    • DDR3/2 LPDDR3/2 PHY- Independent training mode for gate, write leveling
    • 8-bit DQ

Data Sheets are available under NDA

>>>REQUEST NDA

 
 

FPGA Demo


I3C Controller

DTI I3C Controller provides the logic consistent with NXP I3C specification to support the communication of low-speed integrated circuits through I3C bus.
The IP facilitates software controllable by application processor through industry-standard AMBA interface. The bus interface is flexible and easily integrated into APB, AHB or AXI system bus.

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Features Design Status
Compliant with the following specifications:

  • MIPI I3C specification v1.1
  • AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
  • AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
  • AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
  • AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI I3C Controller supports:

  • Two wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C Device co-existence on the same Bus (with some limitations)
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • Legacy I2C messaging
  • I2C-like Single Data Rate Messaging (SDR)
  • Optional High Data Rate Messaging Modes (HDR-DDR, HDR-TSL, HDR-TSP)
  • Support for Multi-master (transferring the ownership of the bus to a Secondary Master if Present)
  • Reception of In-band Interrupt Support from the I3C Slave devices
  • Reception of Hot-Join from newly added I3C Slave devices
  • Synchronous Timing Support and Asynchronous Time Stamping
  • Master only operation
  • Slave only operation
  • Master and slave operation

DTI I3C Master supports:

  • Transmission modes: Single Data Rate (SDR) Mode
  • Dynamic Address Assignment
  • Host-join request
  • Secondary master request to be current master
  • Slave interrupt request
  • Support for I3C common command codes
  • Error Detection and Recovery Methods for SDR

DTI I3C Slave supports:

  • Transmission modes: Single Data Rate (SDR) Mode
  • Dynamic Address Assignment
  • Host-join
  • In-Band Interrupt
  • Error Detection and Recovery Methods for SDR
  • Detect HDR Exit Pattern
  • Support for I3C common command codes:
    • Broadcast CCCs
      • RSTDAA
      • ENTDAA
      • ENEC, DISEC
      • ENTAS0, ENTAS1, ENTAS2, ENTAS3
      • SETMWL, SETMRL
    • Direct CCCs
      • SETDASA
      • SETNEWDA
      • GETSTATUS
      • ENEC, DISEC
      • ENTAS0, ENTAS1, ENTAS2, ENTAS3
      • SETMWL, SETMRL
      • GETMWL, GETMRL
      • GETMXDS
      • GETPID, GETBCR, GETDCR
      • GETXTIME

Data Sheets are available under NDA

REQUEST NDA

 
 

FPGA Demo


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