Direct Memory Access (DMA)
DTI_DMA control the DMA transfers data between different points in the memory space without intervention of the CPU. The DMA is generally used to replace two CPU functions: memory copy and transfer data between memory and peripheral (peripheral devices such as SPI, UART, GPIO, I2C, I2S, WDT, etc.)
Features Design Status
Support 1 to 16 channels (Parameter Configuration)
Support maximum 8 peripherals can connect to 1 DMA channel (Parameter Configuration)
Channel Arbitration
Multiple transfer direction: memory to memory, memory to peripheral, peripheral to memory
Single APB Programming Interface (Programming Registers)
2 AXI4 Master Ports (Parameter Configuration)
AXI4 Data Width: 32, 64, 128, 256 or 512 bits (Parameter Configuration)
AXI4 Address Width: Up to 32 bits (Parameter
Support source address, destination address,
Single FIFO data per channel
Automatic packing/unpacking of data to fit FIFO width
Support timeout monitoring
Data swapping endian mode
Interrupt for DMA transfer and channel status
Support Scatter-Gather mode
Support Circular mode
Support Double Buffer mode
Support 1D-2D transfer mode
Data Sheets are available under NDA
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FPGA Demo
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