The Dolphin UCIe IP (DTI UCIe) provides a complete solution for allowing more data to travel faster between heterogeneous and homogeneous dies in a multi-die package. The DTI UCIe comprises DTI UCIe Controller IP, DTI UCIe PHY and DTI PCIe VIP, delivering maximum bandwidth at data rates up to 16Gb/s. The DTI UCIe PHY supports the link initialization, training, calibration,
power management states, lane repair/mapping and scrambling. The DTI UCIe Controller includes the die-to-die adapter layer and the protocol layer. Designed for low power, low latency and high bandwidth electrical signaling between the dies over multiple substrate types, the DTI UCIe is well suited for data center, AI, automotive applications. In addition, the IP is fully programmable and configurable, flexible to customer’s needs.
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| Features |
Design Status |
DTI UCIe Controller Key Feature:
- Low latency controller for die-to-die data transmission applications.
- Includes die-to-die Adapter Layer and Protocol Layer with support for on-chip interconnect protocols, including CXL, CXS, PCIe and AXI Stream.
- Adapter Initialization.
- Supports both Flit and Raw Mode operation.
- Decision Table for Flit Format and Protocol.
- Multi-stack and Enhanced Multi Protocol.
- ARB/MUX functionality for CXL Protocol.
- CRC or Retry mechanism (when applicable).
- Link State Management.
- Sideband parameter negotiation (through RDI and FDI Sidebands).
- Runtime Link Testing.
DTI UCIe PHY Key Feature:
- Supports standard package and advanced package.
- Support link speed up to 16GT/s.
- Differential clocking only.
- Lane repair (UCIe-A) and width degradation (UCIe-S) to improve manufacturing yield.
- Single-module and multi-module configurations supported.
- Sequential link training compliant with the UCIe 1.1 specification, or selective state training via register configurations.
- Bypass support for Link Training and Setup Controls.
- Complete PHY initialization, training and control.
- Dynamic clock gating and free running clock support.
- Recalibration support (Vendor-defined sideband message).
- Initialization and calibration support for LCDL, DCA and DCD.
- Training support for receive latency, clock positioning, per-bit deskew and VREF.
- Multi-module link support with permitted configuration of one-, two- and four- module links.
- At-speed built-in-self-test (BIST) loopback testing.
- Power-saving features.
- Supports Scan.
DTI UCIe VIP Key Feature:
- Support testbench language for Systemverilog, UVM.
- Protocol check and functional coverage.
- Callbacks, error injection and analysis port for TX, RX driver.
- Support flexiable DUT Types: D2D Adapter, Protocol, Phy, Full Stack.
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