Octa SPI Controller

Dolphin Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices. The Controller and PHY IP connects to a system-on-chip (SoC) host through an AMBA® APB bus for the register interface and optional DMA peripheral interface.

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Features

Design Status

Compliant with the following specifications:

AMBA, Advanced Peripheral Bus (APB) Specification Version 2.0
AMBA, Advanced High-performance Bus (AHB) Specification Version 2.0
AMBA, Advanced eXtensibale Bus (AXI) Specification Version 4.0
AMBA, Advanced eXtensibale Lite Bus (AXI-Lite) Specification Version 4.0

DTI Octal-SPI Controller supports:

JEDEC xSPI standard compliant
Supports flash devices from Micron, Macronix, Spansion …
Supports PSRAM devices from Apmemory
Supports Single/ Octal SPI protocols
Support APB, AHB and AXI interfaces
Single and double transfer rate
Programmable FIFO watermarks
Supports three operating modes: Indirect mode, status-flag polling mode, memory-mapped mode
Interrupt and DMA handler
Data prefetching in memory-mapped mode
Support AHB, AXI and device wrapping bursts
PHY interface with delay locked-loop

Data Sheets are available under NDA

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FPGA Demo

Dolphin Technology Vietnam Center

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