• Fully automated MBIST RTL and Gate flow
• Fully supported BIST test, diagnosis and soft/hard repair
• Fully supported eFuse controller for automated hard repair
• Analyze RTL design or netlist to identify memories
• Plan MBIST engines
• Verify stand-alone
• Insert into RTL design or netlist
• Verify partition level
• Top level hookup to JTAG
• Fully supported P1500 interface and Tap controller
• Verify top level
• Generate test patterns and SVF file
• Incremental repair capability
• Programmable March-style algorithm
• APB interface for BIST test and fuse operation
• Diagnosis test, Characterization test and SVF debug flow
• Fully supported ICL/PDL of IEEE 1687
• Automated subchip integration flow

Data Sheets are available under NDA

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